1. Field of the Invention
The present invention relates to electronic devices, and in particular, to removable and reworkable encapsulated integrated circuit chips and the method of manufacture.
2. Description of Related Art
Surface mount technology (SMT) is a known fabrication process in the microelectronics industry. SMT generally involves forming electronic package assemblies whereby an electrical component, such as an integrated circuit chip, is electrically and mechanically connected to a substrate, a card (i.e., board), another chip or another electronic part.
In one particular application, to which this application is directed to for convenience, multilayer glass-ceramic components, as exemplified by integrated circuit chips on ceramic chip carriers, are joined to printed circuit boards (cards) and/or organic substrates. Often, these multilayer glass-ceramic electronic components are joined to other components by solder interconnections, such as C4 technology or flip chip packaging, or BGA (Ball Grid Array) interconnections, whereby these solder interconnections are made from soldering pads on a surface of a first of these electronic components to corresponding soldering pads on the surface of the second component.
Typical solder surface mount processes involve screening solder paste onto exposed metallic pads of a board or substrate, followed by reflow to bring the solder into spherical shapes. Alternately, solder preforms may be attached to exposed metallic pads by means of flux of solder paste. The reflowed solder or solder ball structure is aligned to corresponding pads on another component, and then the entire assembly is reflowed to melt the solder and create a solder bond between the first and second components. This solder interconnection may be in the form of a ball grid array (BGA), a column grid array (CGA) or a land grid array (LGA).
However, once the solder interconnections are completed, the components may need to be detached from one another. Microelectronics fabrication processes often require disassembly of assembled components, for example, to carry out diagnostic tests, to replace or repair the semiconductor device, to upgrade components, or to recover electrically good substrates from test vehicles or early user hardware used to assess product performance and reliability prior to actual product release.
Removal processes for various assembly materials must be selective for a particular material and cause no detriment to the substrate integrity and electrical performance. It is also required that the removal method be environmentally and chemically suitable for use in a manufacturing environment.
Current approaches for removing electrical components, such as modules containing integrated circuit chips, from organic boards include removal by hot gas. In these hot gas methods, a stream of heated gas, such as N2 or other inert gases, is delivered onto or directed at the electrical component attached to the board via a nozzle. Additional bias heat may be applied via a heating block or heating unit located at the backside of the board to supplement the other thermal inputs.
In these hot gas approaches, heat is transferred through the module and heats up the entire electrical assembly to heat components including, but not limited to, the solder interconnections, lids, heat sinks, chips, underfills, capacitors, and the like. The heat generated at the solder interconnection joining the electrical components to the board liquefies the solder joints allowing such electrical components to be removed from the organic board for rework.
However, by externally applying heat to the electrical component, and optionally the underside of the organic board, certain components within the assembly may be undesirably heated beyond their sustainable temperatures. This external heat may also lead to local hot spots across the board since the hot gas is directed locally on the module that needs to be removed there from. Locally applied heat can also lead to warpage of the organic board as a result of the non-uniform heating of such board. This is undesirable as any board warpage may require that the board be scrapped, along with several other good modules/passives/devices on the board. Further adding to the problems associated with warpage is the placement of heater blocks, or heating units, at the backside of the board as they often interfere with the requirement of holding the board firm and flat. The above problems only get worse as the board size and thickness increase, or when removing large electrical components for rework, such as those having high thermal masses.
Wherein the solder interconnections are lead free solder interconnects, these interconnection schemes generally require the use of higher temperatures during reflow attachment, and even higher temperatures for rework processing. The higher rework temperatures for near eutectic and eutectic lead free solder alloys (Sn/Ag, Sn/Ag/Cu, Sn/Cu), typically range from about 217° C. to about 227° C., and may be higher for hyper-eutectic compositions of the foregoing alloys, such as at temperatures above 227° C. or greater. Yet, these higher rework temperatures for lead free solders can irreparably damage the organic board, and as such, rework of lead free alloy containing assemblies has become a critical issue in the qualification of this technology.
Therefore, a need continues to exist in the art for providing improved methods and structures for the rework of electronic assemblies, and in particular for the removal of electronic components joined to organic boards by solder interconnections for their subsequent use and re-use in integrated circuit fabrication processing.